2024 · NVIDIA · ASIC Design Intern(上海) 笔试

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题目	题型	难度	标签
Implement an AND gate with a 2-to-1 MUX.	问答题	中等	2024秋招笔试真题Online AssessmentNVIDIA ASIC Design I
The glitch before a 2D synchronizer could cause wrong data signal on destination domain. How to reduce the glitch before	单选题	中等	2024秋招笔试真题Online AssessmentNVIDIA ASIC Design I
There's an asynchronous FIFO between the source and destination clock. The source and destination clock run at the same	单选题	中等	2024秋招笔试真题Online AssessmentNVIDIA ASIC Design I
How to fix hold time violation?(select all applicable) Pick ONE or MORE options	多选题	中等	2024秋招笔试真题Online AssessmentNVIDIA ASIC Design I
Which common power mechanisms cannot save static power? (select all applicable) Pick ONE or MORE	多选题	中等	2024秋招笔试真题Online AssessmentNVIDIA ASIC Design I
Implement a module to delay a 1-bit sequence by 16 cycles:	编程题	中等	2024秋招笔试真题Online AssessmentNVIDIA ASIC Design I
Implement a 10-to-1 multiplexer with three 4-to-1 multiplexers. 0000 can select din0, 0001 can selelct din1, ..., 1000 c	编程题	中等	2024秋招笔试真题Online AssessmentNVIDIA ASIC Design I
Implement a combination logic for dout[1:0] = din[2:0]/3. (The more options, the better)	编程题	中等	2024秋招笔试真题Online AssessmentNVIDIA ASIC Design I